One type of conventional high power FET is formed by creating long rows of alternating source and drain regions separated by a channel region. A gate overlies the channel region. The gate width is thus very large to create a high current FET. The source and drain regions are the same conductivity type, and a threshold voltage on the gate creates a conductive channel between the source and the drain to conduct current. Such a transistor is a lateral FET. Narrow metal strips contact and interconnect the source regions, and other metal strips contact and interconnect the drain regions.
Another type of high power lateral FET forms cells of source and drain regions separated by a channel, where a gate overlies the channel. Each adjacent cell pair forms a single transistor, and the cells are all connected in parallel by narrow metal strips to conduct a high current.
High power FETs may also be vertical transistors, using double diffusion, where the doped regions formed in the silicon surface are all source and channel regions, and a voltage on the gate inverts the channel region. The current path is then vertical, where the drain is the bottom surface of the silicon substrate. A metal layer contacts all the source regions. Another type of vertical FET uses a vertical gate.
Various types of high power FETs are described in U.S. Pat. No. 5,355,008, co-invented by the present inventor and incorporated herein by reference.
In very high power FETs, such as those conducting one amp or more, the high current creates a significant voltage drop across the metal overlying and contacting the doped regions, due to the inherent resistivity of the metal layer. Although the on-resistance can be lowered by making the metal thicker, problems arise in masking, etching, and passivating such thick metal. Additionally, the same metal layer may be patterned for interconnecting components of low power circuitry formed on the same chip as the high power FET, and a thick metal layer would undesirably increase the minimum possible line width.
One solution for lowering the on-resistance is creating an insulating layer over the first-layer metal strips (formed by a first metal layer) and forming vias (small holes) in the insulating layer over portions of the first-layer metal strips. A wide metal source bus strip (formed by a second metal layer), perpendicular to the narrow source metal strips, is then formed over the insulating layer and in the vias to provide a low resistance coupling to each of the first-layer source metal strips. A similar wide drain metal bus strip may be formed to contact the first-layer drain metal strips.
Although the wide bus strips reduce on-resistance, there are significant drawbacks in making the bus strips thick. Firstly, depositing, masking, and etching a thick metal is time consuming. Secondly, the second metal layer may be patterned for interconnecting other circuits, and a thick metal layer increases the minimum possible line width. Thirdly, it is difficult to thoroughly passivate a thick metal layer due to the high step.
Forming additional overlying metal layers, connected to the underlying metal with vias through an insulating layer, for further reducing on-resistance similarly require substantial time to deposit, mask, and etch the metal. Additionally, the small vias incur some voltage drop due to their small cross-sectional area.
What is needed is a simple technique to form thick metal conductors overlying a high power FET for conducting source or drain current.